Pin outs for the Audigy2 chips.
E.g. CA0108, CA10300 etc.

Left	
1	IN_MIDI_A
2	SDA0
3	SL0
4	SCS
5	SCLK
6	VSS (Chip ground)
7	SDA
8	SDAIN
9	JOY_CMP0 (analog)
10	JOY_CMP1 (analog)
11	JOY_CMP2 (analog)
12	JOY_CMP3 (analog)
13	VDD (Chip power 1.8V)
14	JOYPB0 (switch pull-up)
15	JOYPB1 (switch pull-up)
16	VDDIO (IO power 3.3V)
17	VSS (Chip ground)
18	JOYPB2 (switch pull-up)
19	JOYPB3 (switch pull-up)
20	JOY_TRIGN (Output)
21	VDD (Chip power 1.8V)
22	INTAN (PCI Interrupt active low)
23	PCIRSTN (PCI bus reset IN)
24	VSS
25	PCICLK (PCI bus clock IN)
26	GNTN (PCI bus grant not IN)
27	VDDIO (IO power 3.3V)
28	REQN (PCI request not OUT)
29	AD31 (PCI addr)
30	AD30
31	VSS
32	AD29
33	AD28
34	AD27
35	VIO5V (Pads biasing 5V)
36	AD26
37	AD25
38	AD24
39	VSS
40	CBEN3 (PCI command byte enable)
41	IDSEL (PCI device select for configuration)
42	AD23
43	VDD
44	AD22
	
Bottom	
45	AD21
46	AD20
47	AD19
48	VSS
49	AD18
50	AD17
51	AD16
52	CBEN2 (PCI command byte enable)
53	FRAMEN (PCI frame, active low)
54	VDDIO
55	IRDYN (PCI Initiator Read Signal, Active low)
56	TRDYN (PCI Target Ready, Active low)
57	DEVSELN (PCI Target Device Select Not)
58	STOPN (PCI STOP Transfer Control Signal, Active low)
59	PERRN (PCI Parity Error Report Signal. Active low)
60	VSS
61	SERRN (PCI System Error Report, Active low)
62	PAR (PCI Bus Parity)
63	CBEN1 (PCI command byte enable)
64	VDD
65	AD15
66	VIO5V
67	AD14
68	AD13
69	AD12
70	AD11
71	VSS
72	AD10
73	AD9
74	AD8
75	CBEN0
76	VDDIO
77	AD7
78	AD6
79	AD5
80	AD4
81	VSS
82	AD3
83	AD2
84	AD1
85	VDD
86	AD0
87	VIO5V
88	SCANCLK (In)
	
Right	
89	SCANEN (In pull-down)
90	EESDO/I2C_SDA (Serial Host Data to EEPROM, Out )
91	VSS
92	EESDI (In)
93	EECLK/I2C_SC (EEPROM Interface Bit Clock, Out)
94	EECS (Out)
95	EE_Sel (EEPROM Select)
96	E32FSON (Out)
97	VDDIO
98	E32IND1 (In)
99	E32IND0 (In)
100	E32OBC (Out)
101	E32OD1 (Out)
102	VSS
103	E32OD0 (Out)
104	E32OCCN (Out)
105	MFSIN (In)
106	I2SINLR0 (Left Right for I2S Input, Bi-directional)
107	I2SINBCLK0 (Bit Clocks for I2S Input, Bi-directional)
108	VDD
109	I2SIN0 (In)
110	GPI0   (General Purpose input)
111	IN_MIDI_B
112	OUT_MIDI_B
113	VDDIO
114	GPI1  (General Purpose input)
115	SPDIFO2 (SPDIF Output)
116	VSS
117	SPDIFO1 (SPDIF Output)
118	SPDIFO0 (SPDIF Output)
119	SPDIFO3 (SPDIF Output)
120	GPO0 (General Purpose output)
121	GPO1 (General Purpose output)
122	VSS
123	GPO2 (General Purpose output)
124	SPDIFIB (SPDIF Input)
125	VOL_INC_N (In)
126	VOL_DEC_N (In)
127	PLLVDD (PLL Power)
128	XO (Crystal Oscillator output)
129	PLLVSS (PLL Ground)
130	XI (24.576 MHz Clock from Oscillator or crystal)
131	VDD
132	SPDIFIC (SPDIF Input)
	
Top	
133	SPDIFIA (SPDIF Input)
134	GPI2 (General Purpose input)
135	I2SIN2 (Data In)
136	I2SINBCLK2 (Bit Clocks for I2S Input, Bi-directional)
137	VSS
138	I2SINLR2 (Left Right for I2S Input, Bi-directional)
139	I2SIN1 (Data In)
140	I2SINBCLK1 (Bit Clocks for I2S Input, Bi-directional)
141	VDDIO
142	I2SINLR1
143	I2SIN_MCLK (Master Clock for I2SIN ADC)
144	GPI3
145	VSS
146	GPI4
147	B_RESET (Out)
148	IDDQPC (Input)
149	GPI5
150	VDD
151	GPO3
152	GPO4
153	GPO5
154	GPO6
155	VSS
156	IRIN (In, Pull-up)
157	TEST (In, Pull-down)
158	GPO7
159	I2SOUTBCLK (Bit Clocks for I2S Output, Bi-directional)
160	I2SOUTLRCLK (Left Right for I2S Output, Bi-directional)
161	I2SOUT0 (Data out)
162	I2SOUT1 (Data out)
163	VSS
164	I2SOUT2 (Data out)
165	I2SOUT3 (Data out)
166	CLK256FS (256 * Sample Rate Output)
167	VDDIO
168	AC97SYNC (Sync Output to AC97 CODEC)
169	AC97BCK (AC97 Bit Clock)
170	VSS
171	AC97SDI (Serial Data Input from AC97 CODEC)
172	AC97SDO (Serial Data Output to AC97 CODEC)
173	AC97RSTN (Reset Not to AC97 CODEC, Output)
174	CLK24MHz_Out (Buffered Clk 512, Approx.24.576MHz. Same as crystal)
175	VDD
176	OUT_MIDI_A